AMD flips the chook at Intel because it glides previous in CPU-GPU stakes

AMD is speaking up inside engineering advances because it appears ahead to the introduction of its first hybrid CPU-GPU datacenter chip and extra Epyc merchandise, simply as rival Intel confirms delays to its personal GPU lineup.

Talking on the Morgan Stanley Know-how, Media and Telecom convention, AMD CTO Mark Papermaster pointed to the progress the corporate is making with the Intuition MI250 accelerator and its successor, the MI300.

Papermaster mentioned AMD had began growth of the Intuition GPUs when the corporate noticed “the place AI was heading,” and this could possibly be accelerated by parallel and vector processing.

“We centered first on HPC as a result of we had an excellent software program stack already to construct on. It is known as the ROCm stack. And so ROCm 4.0 was launched a few years in the past that was manufacturing degree for HPC. And having this sort of modern {hardware} and a manufacturing HPC stack led to key wins throughout the HPC sector,” he claimed.

ROCm 5.0 added help for PyTorch, TensorFlow and different machine studying frameworks, and is now manufacturing degree for AI processing, he mentioned.

“If you happen to go to PyTorch, you see solely two software program stacks rated at manufacturing degree on Linux, and that’s AMD and our GPU competitor Nvidia,” Papermaster claimed.

The MI250 has been accessible for a few yr now and AMD has talked in regards to the next-generation chip, the MI300, since about final June, so what is occurring with that?

“We’ll be saying that second half of this yr, and ramping in 2024,” Papermaster acknowledged, describing the corporate’s hybrid CPU-GPU chip as “a beast.” That is as a result of “it takes 4 GPU CPUs – 4 Genoa CPUs – and embeds it with our graphics processing,” he defined.

Meaning CPU cores primarily based on the 4th Gen Epyc structure mixed with a GPU primarily based on the next-gen CDNA 3 structure, as detailed beforehand.

Papermaster in contrast this to AMD’s earlier accelerated processing unit (APU) chips for shopper units, which mixed CPUs and client GPU features gained from its acquisition of ATI.

“Similar to we shipped mixed CPU and GPU for years in PC and embedded markets, we have now introduced that strategy to the datacenter with the Intuition 300,” he mentioned, including that AMD is primarily focusing on hyperscalers, reasonably than making an attempt to hit each single vertical market with its accelerator merchandise.

The MI300 was to have confronted a brand new GPU product from rival Intel, Rialto Bridge, which was because of begin sampling to distributors in the course of this yr. Nonetheless, this has now been canned, as Intel disclosed final week, and Falcon Shores, Intel’s personal CPU-GPU chip with x86 CPU cores and Xe GPU cores, is now delayed till 2025.

Papermaster additionally briefly talked about Siena, one other upcoming member of AMD’s 4th Gen Epyc server processor household that may goal edge computing and telecoms use circumstances.

Siena might be “a telco optimized model of our fourth-generation Epyc popping out second half of this yr,” he mentioned, and talked up the synergy he noticed between this and the telecoms portfolio AMD gained from its buy of Xilinx, which the corporate had on present on the current Cellular World Congress occasion in Barcelona.

“With the appearance of 5G, AMD now has an end-to-end from the management airplane with the presence we already had with our Epyc product line,” Papermaster mentioned.

Siena is anticipated to have as much as 64 Zen 4 cores and might be optimized for performance-per-watt, however in any other case it is not clear what options it must make it higher fitted to telecoms purposes. Intel’s Xeon D household has built-in networking and high quality of service (QoS) features, for instance.

Papermaster was additionally requested about Inspur, the China-based OEM that was lately added to the entity checklist of restricted distributors by the US Division of Commerce. Inspur provides servers to many cloud suppliers and HPC prospects, and has hyperlinks with most of the large US tech firms.

“Like everybody in our trade, we in fact comply with all the tips of export controls from the US authorities, together with the Entity Checklist,” he mentioned. “We’re searching for clarification as I feel the remainder of the trade is, as a result of Inspur is a big holding firm. It serves many markets. So, we’re trying to get clarification on these tips.”

Papermaster additionally spoke about Moore’s Regulation, as he has carried out at earlier occasions, and mentioned that processor firms needed to adapt to the slowing of enhancements in transistor density.

“Course of know-how is foundational in our semiconductor trade,” he mentioned, “however Moore’s Regulation, it is slowing down. The price of transistors goes up per node. The kind of scaling you get, the kind of circuitry that will get the profit out of every new know-how node is getting much less. Among the circuit varieties do not scale.”

Which means a chip design and the method know-how actually must be developed carefully collectively greater than ever earlier than, in line with Papermaster, and that is what led AMD to a modular strategy such because the Infinity structure, which permits the partitioning out of various circuit varieties to completely different course of nodes.

“That mentioned, the brand new nodes stay vitally essential,” he defined. “These transistors wish to function on the most effectivity you possibly can. And that is what every know-how new node brings. The transistors and the brand new nodes are getting dearer, however they’re nonetheless providing you with effectivity positive factors, extra efficiency at much less watts of vitality expended.” ®